A multi-port latch is a storage element that selects one piece of write data from a plurality of pieces of write data and stores the selected write data. A widely known dual port memory is a memory that selects one piece of write data from two pieces of write data and stores the selected write data.
There is limitation that a plurality pieces of write data are not allowed to be selected at the same time and written in the multi-port latch. When the plurality pieces of write data are selected at the same time and written in the multi-port latch, bus fight (short circuit) may occur in a storage unit. When the bus fight occurs, a value to be stored is not determined, and there occurs a problem that large current flows into the storage unit and breaks down a semiconductor device in the storage unit at worst. The occurrence of one signal that is used to select data to be written is referred to as one hot, and the occurrence of a plurality of signals that are used to select data to be written at the same time is referred to multi-hot.
A register file device in which the multi-port latch is used is controlled so that multi-hot does not occur. Therefore, the occurrence of multi-hot means that an error has occurred in the device, and it is desirable to execute some recovery processing, and recovery processing to be executed is set as appropriate.
In addition, when multi-hot occurs, bus fight occurs in the multi-port latch, and the semiconductor device of the storage unit may be broken down. When the semiconductor device is broken down, the multi-port latch becomes unrecoverable and is not allowed to be used thereafter. In order to avoid such a situation, it has been proposed measures for avoiding the occurrence of bus fight are taken for write signals of the multi-port latch in the register file device.
In one of the proposed measures, a priority adjustment circuit is provided that adjusts priority of write control signals in a unit of access of the multi-port latch, for example, in a unit of word of the multi-port latch to prohibit multi-hot so that one data selection signal is merely output once. However, in such a measure, the priority adjustment circuit is provided for each word in the multi-port latch, so that there is a problem that the footprint is increased undesirably. In addition, the priority adjustment circuit is provided at the downstream of a decoder circuit of an address for accessing the multi-port latch, so that there is a problem that delay of a write path is increased, and the operation speed becomes slow.
In the other measure, a 1-hot guarantee circuit is provided that checks whether address values for accessing the multi-port latch are matched to each other and stops decoding of the corresponding address when the address values are matched to each other, to guarantee that 1-hot or less occurs. In the other measure, the single 1-hot guarantee circuit is provided in the register file device, so that an increase in the footprint is suppressed. However, the 1-hot guarantee circuit is provided at the upstream of a decoder circuit of an address for accessing the multi-port latch, and an operation of the decoder circuit is controlled depending on the result that is obtained in the 1-hot guarantee circuit, so that there is a problem that delay of the write path is increased, and the operation speed becomes slow.
The following is reference documents:    [Document 1] Japanese Laid-open Patent Publication No. 2007-018501 and    [Document 2] Japanese Laid-open Patent Publication No. 2003-091992.